1. Technical Field
The present invention relates to an ESD (Electro-Static Discharge) protection circuit with EOS (Electric Over-Stress) immunity, more particularly, to an ESD protection circuit immune to erroneous triggering of EOS to achieve both ESD protection and EOS immunity.
2. Description of the Related Art
Dice, chips and integrated circuits have become the most important hardware bases of modern information society. A chip is equipped with I/O interface to exchange information with other circuits (e.g., circuit boards and/or other chips); however, as the I/O interface directly contacts electronic environment external to the chip through conductive structures like pads, pins and/or solder balls, abnormal electronic events conduct to the chip through the I/O interface to cause malfunctions and/or damages.